Wednesday, 9 November 2016

[23404MSCRMCV] Validation Engineer- Santa Clara, CA- 6+months

Hi ,


Please let me know if you any consultant available for the following role.

And please reply to


System Design Engineer- Validation Engineer

Santa Clara, CA



System design engineer – 2.5G/5G/10GBase-T Transceiver Post Silicon Validation


Job Description:

Validation Engineer will be responsible for system level functional and channel/cable performance validation, device level characterization and performance/power optimization of 2.5G/5G/10GBASE-T Transceivers.  Responsibilities include creating test plan, developing automation test frameworks, executing tests and generating test reports. Engineers will also be working with other teams on all aspects of issue debugging and resolving.



MSEE preferred

Must have prior experience with validation and/or development of Ethernet transceiver.

Must have solid understanding and working experience of IEEE802.3 specification covering 10Gbase-T, 2.5G/5GBase-T, 1000Base-T, 100Base-T and 10Base-T, as well as 100/40/10GBase-R technologies.

Must have knowledge and working experience in high speed signal design and characterization.

Must have solid knowledge in both digital and analog design.

Much desirable to have good understanding of DSP fundamentals.

Demonstrated ability in developing functional and performance validation/electrical characterization of complex mix signal ICs.  Knowledge spans both digital and analog discipline.

Must have strong skill in test automation using programming languages like Matlab, Labview, TCL, VB and C language.  

Much desirable to have experience of lab and test equipment including oscilloscope, spectrum analyzer, network analyzer, waveform generator, and traffic generator.

Must have excellent communication and problem solving skill sets.



Thanks & Regards,


Manoj Singh

Technical Recruiter | Direct: 408-844-3513

IDC Technologies, Inc

1851 McCarthy Boulevard, Suite 116, Milpitas, CA, USA, 95035.



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